The present invention relates in general to communication systems and subsystems therefor, is particularly directed to a digital delay line-based phase detector, which is operative to generate a digital output code that is representative, to a very high resolution in increments of the delay of a digital gate (e.g., nanoseconds), of the timing relationship (e.g., phase difference) between two signals, such as relatively lower frequency local clock and reference clock signals.
A common requirement of communication systems, such as, but not limited to, digital telecommunication systems and networks, is the precision alignment (phase-locking) of a pair of (clock) signals, one of which may be derived or extracted from an external source, such as a received signal, and the other of which is locally generated, such as a reference oscillator of a phase locked loop (PLL). FIG. 1 diagrammatically illustrates a reduced complexity prior art phase difference architecture employed for controlling the output frequency of a phase locked loop-based clock recovery circuit.
This prior art circuit incorporates an exclusive-OR circuit-based phase detector 10, the output of which is coupled to an analog low pass filter 12 to derive an analog value representative of the phase difference between two clock signals applied to the phase detector 10. This analog phase difference value is quantized by an analog-to-digital converter (ADC) 14 to provide a digital phase word. The digital phase word is then coupled to a digital filter 16, which performs a low pass filtering function and applies its output to a digital-to-analog converter (DAC) 18. The output of the DAC 18 is used to control the output frequency produced by a voltage controlled oscillator (VCO) 19.
A fundamental shortcoming of this type of circuit is the fact that it uses an ADC to digitize analog phase information. In the first place, not only are precision ADCs costly, but analog components are subject to variations due to changes in temperature, aging, and the like. Also, it is difficult to achieve high phase resolution over a wide range of phase difference between the two clock signals.
Direct digital synthesis (DDS) techniques, which derive a variable frequency, phase-locked clock from a fixed frequency oscillator, offer a significant improvement over the conventional approach of FIG. 1, since a DDS scheme is able to provide a very high resolution clock phase from a relatively low cost fixed frequency oscillator; however, the resulting jitter must be filtered using a wide bandwidth analog phase-locked loop. In addition, a relatively high order analog anti-aliasing low pass filter is usually installed downstream of the DDS"" DAC prior to a comparator, which samples the analog signal and outputs the digital clock.
For examples of patent documentation which illustrate various prior art schemes including those described above, attention may be directed to the U.S. Pat. Nos: 5,638,410; 5,084,669; 5,220,275; and 5,790,614.
In accordance with the present invention, shortcomings of conventional phase detection schemes are effectively obviated by a digital delay line-based timing relationship detector. This detector is configured to generate a digital code representative of the phase difference between two signals, as a combination of a first, most significant phase word (or MSPW), and a second, least significant phase word (or LSPW). The value of the MSPW is produced by a first code generator in accordance with the number of high frequency clock signals counted between transitions in a first (low frequency) local clock signal (termed an LF LOCAL CLOCK signal) and a second, low frequency reference clock signal (termed an LF REF CLOCK) to within one cycle of a prescribed high frequency (HF) clock signal. By high frequency clock signal is meant a clock signal whose frequency is considerably higher (e.g., several orders of magnitude or greater) than those of the low frequency local and reference signals whose phase differential is to be determined. The frequencies of the low frequency local and reference signals are typically approximately the same.
The LSPW is produced by a delay line phase sampler (DLPS), which functions as a second digital code generator.
The value of the LSPW is defined by the number of stages of a multistage digital delay line/shift register, through which a digital value associated with a transition in one of the two signals propagates until the next transition in the high frequency clock signal. At this transition, the location of the digital value is frozen in the delay line/shift register, and the delay line/shift register is configured to operate in shift register mode. As the contents of the shift register are sequentially clocked out, the contents of a counter are sequentially modified to realize the value of the LSPW.
The first digital code generator contains a K-bit phase down-counter, whose contents are decremented one count for each HF clock period, from a preloaded (high) count to a low count. A high count represents a +180xc2x0 phase value, a mid count represents a 0xc2x0 phase value, and a low count represents a xe2x88x92180xc2x0 phase value. The most significant bit of the K-bit phase word within the down-counter represents the polarity of the phase. The low frequency local clock signal is generated in alignment with and as an integral multiple of (typically several orders of magnitude lower in frequency than) the HF clock. The sequentially decremented count value within the phase down-counter is controllably loaded into a K-bit MSPW latch of a digital code combiner. The contents of the K-bit latch are controllably transferred to an intermediate K+L bit phase word latch upstream of an output K+L bit phase word latch.
The most significant bit (MSB) of the mid count value of the K-bit count in the phase down-counter (as advanced by two HF clock periods) is used to produce the LF LOCAL CLOCK signal. The DLPS compares the LF REF CLOCK signal and the HF clock signal, in order to provide a very precise measure(in terms of a fraction of an HF clock cycle) of the relative timing differential between the LF LOCAL CLOCK signal and the LF REF CLOCK signal. It then supplies a LATCH MSPW output pulse to the K-bit latch, which loads the contents of the K-bit phase down-counter as a K-bit MSPW.
Some number (one to 2L) of HF clocks subsequent to a prescribed transition (e.g., rising edge) of the LF REF CLOCK signal, the DLPS outputs a stable L-bit LSPW word representative of the relative timing differential between the rising edge of the LF REF CLOCK signal and the next rising edge of the HF clock signal. The DLPS then supplies a LATCH PW pulse to the intermediate K+L bit phase word latch, so that the K-bit MSPW from the K-bit latch and the LSPW word from the DLPS are loaded as a K+L bit phase word into the intermediate K+L bit latch. It also controls the transfer of the K+L bit phase word in the intermediate latch to an output latch. The K+L output bit phase word in the output latch is a binary representation of the phase position of the rising edge of the LF REF CLOCK signal with respect to the rising edge of the LF LOCAL CLOCK signal.
The DLPS includes a multistage digital delay line/shift register formed of a cascaded arrangement of flip-flops interleaved with selector gates. The overall length of the delay line/shift register provides an effective electronic propagation delay equal to or greater than the period of one HF clock signal. The delay line is coupled to the output of a multibit input shift register, to which the LF REF CLOCK signal is supplied. Front end stages of the delay line/shift register are coupled through an OR gate to produce a shift delay line signal SHIFT DL, which controls the selector gates, and is used to generate the LATCH MSPW pulse. The last stage of the delay line/shift register is used to generate END SHIFT and COUNT signals that are used to control the operation of an LSPW up-counter from which the L-bit LSPW is derived. The LATCH PW is delayed by the END SHIFT signal for controlling loading of the MSPW AND LSPW into the K+L intermediate latch.
When a transition (e.g., rising edge) of the LF REF CLOCK signal is sampled, a xe2x80x981xe2x80x99 bit propagates through the selector gates of successive stages of the delay line/shift register, which initially is controlled so as to operate as a delay line. Upon the rising edge of the next HF CLOCK signal, the shift register latches the effective propagation delay length. Upon the rising edge of the next HF clock signal, the operational state of the delay line/shift register converts to a shift register, so that its contents may be read out via the LSPW up-counter. The contents of the LSPW up-counter are then sequentially incremented by further HF CLOCK signals. Once the rightmost xe2x80x981xe2x80x99 bit is clocked into the last stage of the delay line/shift register, the logic state of the COUNT signal terminates incrementing the contents of LSPW up-counter, and further shifting of the delay line/shift register. The up-counter now contains a binary value representative of the fractional HF cycle phase delay. Through inverters this binary value is converted into the LSPW.
To ensure that under the conditions of fast propagation times, the number of selector gates is typically greater than that required to provide a single HF CLOCK period delay. This creates a nonlinear phase mapping of the LSPW with respect to the MSPW. There is a discontinuity in the rollover of the LSPW count to or from a zero count, as the MSPW is incremented or decremented by one count. However, the value of the phase word will always increase or decrease monotonically, as the LF REF CLOCK signal phase is advanced or retarded relative to the LF LOCAL CLOCK signal. In some phase-locked applications, monotonic phase mapping containing discontinuities is acceptable. However, for applications that require improved linearity, periodic calibration can be used to linearize the LSPW values. The LSPW linearizer conducts a periodic calibration to determine one HF CLOCK signal period delay LSPW unscaled count. This count, termed a CAL count, is used to scale or multiply by a scaling factor all LSPW values up to the full 2Lxe2x88x921 count range. The LSPW scaler performs the multiplication: LSPW scaled=2Lxe2x88x921/CAL COUNTxc3x97LSPW UNSCALED.
Calibration is performed by substituting a calibration clock rising edge for a LF REF CLOCK signal rising edge to the DLPS at periodic intervals, with the interval to ensure insignificant delay drift due to integrated circuit temperature and supply voltage variations. During the calibration cycle, the previous value of the LSPW is output and the CAL count value is updated. If the digital, delay line-based, timing relationship detector of the invention is employed in an application where the phase of the LF REF CLOCK signal varies continuously by more than a single period of the HF CLOCK signal, it is only necessary to periodically detect the maximum value of the LSPW count and latch this maximum value as the CAL count. No calibration cycle, which results in a loss of one LSPW sample, is necessary.